Ultimate Performance IP for your FPGA. Every Bit Counts.

Specialist Ethernet Software for Xilinx FPGAs. Maximise the performance of your FPGA with our established, secure, high speed data transfer IP cores featuring our patent- pending authentication software.

Innovate. Accelerate. Integrate.

Rely on Chevin Technology’s adaptable Ethernet IP for consistent, high speed data transfer in your FPGA design. Benefit from our expert Engineering Design Consulting and support services to achieve optimum results for your project.

TCP/IP

10 & 25Gbit/s TCP Offload Engine for FPGAs

UDP/IP

10G & 25G Ethernet UDP/IP Offload Engine for FPGAs

MAC/PCS

10& 25G MAC/PCS for FPGAs

Technology

Xilinx FPGAs & accelerated applications

The Specialist IP Core Provider


Chevin Technology delivers high performance, configurable Ethernet IP Cores for Xilinx FPGAs. Our goal is to provide reliable, hardware accelerator capabilities for high end FPGAs that are cost effective and straightforward to implement into client’s projects, using a minimum of FPGA resources. Our Ethernet IP cores are developed and comprehensively tested in-house, so we can offer valuable, expert knowledge and responsive engineering support to smooth the path for successful integration into client products.

Chevin Technology’s IP Cores achieve high throughput and sustained data rates to maximise link utilization. The compact, ‘all logic’ architecture requires no CPU/SW, therefore reducing complexity, latency and energy consumption, while leaving maximum space for further design logic on customer FPGAs. Chevin Technology’s Ethernet IP Cores also feature our patent-pending Authentication Server, which provides further design flexibility and cost efficiency, as clients have the option of adding extra features as required throughout the design cycle. Client projects include scientific research, international defence; medical research, industrial imaging, data storage.

Circuit,Board

Reliable Hardware Accelerator Ethernet IP for FPGAs

Latest Updates


10 November 2021

Domain Specific Computing with FPGAs

The continued watering-down of Moore’s Law means that performance gains cannot be gained with a simple “Scale Up”, using a CPU with a higher clock rate.

21 October 2021

NVMe over TCP

Demand for high performance compute and memory is becoming increasingly difficult to scale, as throughput, latency and capacity demands for both are harder to meet.

21 October 2021

Reference Design

Evaluate CT’s Ethernet IP on your FPGA using our reference design