MAC/PCS

Smooth integration of TCP/IP and UDP/IP protocols in your FPGA

Key features and benefits


  • 10/25Gbit Ethernet Connectivity in Xilinx FPGA
  • Designed to IEEE 802.3by specification
  • Low latency, TX 11ns, RX 8ns (Modes: cut-through/store-and-forward)
  • Integrated FCS(CRC32) checker and generator
  • Small Footprint, Virtex UltraScale 2680 LUTs / 2 Block RAMs
  • Pause packet generate/accept
  • Deficit Idle Control / Programmable IFG, less gaps, more throughput
  • Store-and-forward /Cut-Through FIFO modes for minimum workload/latency
  • Statistics counters, TX and RX traffic stats collected in size bins, frame type, FCS errors
  • Local/Remote fault handling at RS Sub-Layer
  • MAC Filter/Promiscuous Mode
  • Easy to integrate, simple host interface to registers and statistics table.

Options

  • Xilinx AXI4 streaming interface
  • VLAN 802.1Q & PFC priority flow control
  • IEEE 1588 Precision Time Protocol
  • Advanced Hash Table based Filters, MAC address, IP, TCP/UDP port
  • Encrypted Netlist

Lower Layer IP Blocks Network Side

  • Connect to SFP28 (copper Direct Attach or optical Fibre) with Chevin Technology 25GPCS (PCS-PMA,25GBASE-R)
  • Connect to back-plane

Upper Layers IP Blocks Application Side

  • Add RTL-hardened functions for ICMP and ARP to any application using XGARP/ICMP

Contact us for datasheet and pricing

mac-1

Ethernet Mac

10 & 25Gbit/s Ethernet PCS/PMA


PGA Synthesisable 10/25Gbit/s Ethernet PCS code for ultra-low latency 10/25Gbit/s connectivity 1025GBASE-R

The 10/25GPCS IP block simplifies FPGA integration of an ultra-fast 10/25Gbit/s Ethernet PCS Layer in FPGA

IEEE802.3by specification for coding/decoding using 64b66b rules, scrambling with a powerful polynomial and gearbox

Proven on Alpha-Data ADM-PCIE-8V3 board to reduce PCS latency down to 42.3ns/99ns between XGMII and XSBI interfaces.

Key Features

  • 10/25Gbit Ethernet Connectivity in Xilinx FPGA
  • Designed to IEEE 802.3by specification
  • 10Gbit/s Low latency, 109 ns Round trip time, XGMII -> Wire -> XGMII
  • 2404 LUTs
  • 25Gbit/s Low latency, 99 ns Round trip time, XGMII -> Wire -> XGMII
  • 5250 LUTs
  • Integrated 64b66b codec, scrambler/descrambler and gearbox 66/32bit
  • Fault management
  • BER monitoring
  • PRBS pattern generator/checker
  • Statistics block

Options

  • Encrypted Netlist
  • XGMII Interface to MAC directly or via XAUI

Contact us for datasheet and pricing

pcs

Ethernet PCS/PMA